Validation coverage analysis for complex digital designs

The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the testvector suite covers the important tests is known as the coverage of the suite. Previous coverage metrics have relied on measures such as the number of simulated cycles or number of toggles on a circuit node, which are indirect metrics at best. This paper proposes a new method of analyzing coverage based on projecting a minimized control finite-state graph onto control signals for the datapath part of the design to yield a meaningful metric and provide detailed feedback about missing tests. The largest hurdle is state-space explosion. We describe two methods of dealing with this in a practical manner and give results of applying this coverage analysis to parts of the node controller of the Stanford FLASH multiprocessor.

• Type: Conference
• Year: 1996
• Where: ICCAD
• Authors: Richard C. Ho, Mark Horowitz
• Keywords: Control Finite-state Graph, Hardware, ICCAD 1996, Indirect Metrics, State-of-the-art Digital Design