Metrology for analog module testing using analog testability bus

In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic eects in an analog testability bus test environment. For the test response analysis, we derive an extraction methodology to remove the parasitic eects and obtain the intrinsic response of the CUT. The test results show that the algorithm is robust such that the intrinsic responses remain the same regardless of the small variation in the test waveforms. With the concept of intrinsic responses, we are able to use a single library for the testing and diagnosis of multiple instantiation of an analog module.

• Type: Conference
• Year: 1996
• Where: ICCAD
• Authors: Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting
• Keywords: Hardware, ICCAD 1996, Intrinsic Responses, Test Waveforms, Testability Bus Test