A performance evaluator for parameterized ASIC architectures

System-levelpartitioning assigns functionalobjects such as tasks or code segments to system-level components such as o-the-shelf processors or application-specic architectures in order to meet design constraints. Characterization of these system-level components and performance evaluation of given applications on these components are crucial to system-level partitioning. In this paper, we propose a new parameterized architecture model of system-level components and present an algorithm for rapid performance estimation. The model, dierent from those proposed previously, re ects comprehensive architecturalcharacteristics aecting machine parallelism. By using an ultra-ne-grain scheduler which exploits the parallelism in the model, we can evaluate performance of applications assigned to various architectures.

• Type: Conference
• Year: 1994
• Where: EURODAC
• Authors: Jie Gong, Daniel D. Gajski, Alex Nicolau
• Keywords: EURODAC 1994, System-level Components, System-level Partitioning, System-levelpartitioning Assigns Functionalobjects, VHDL