Mapping to Reduce Contention in Multiprocessor Architectures

Reducingcommunicationoverheadhas been widely recognized as a requirement for achieving efficient mappings which substantially reduce the execution time of parallel algorithms. This paper presents an iterative heuristic for static mapping of parallel algorithms to architectures. Special attention is given to measuring and reducing channel contention. Experimental results are used to show the effects of channel contention for packet-switched networks and the improvement realized by our heuristic. We also present preliminary results for wormhole-routednetworks.

• Type: Conference
• Year: 1993
• Where: IPPS
• Authors: Loren Schwiebert, D. N. Jayasimha
• Keywords: Channel Contention, Distributed And Parallel Computing, Efficient Mappings, IPPS 1993, Parallel Algorithms