Leo: a system for cost effective 3D shaded graphics

A physically compact, low cost, high performance 3D graphics accelerator is presented. It supports shaded rendering of triangles and antialiased lines into a double-buffered 24-bit true color frame buffer with a 24-bit Z-buffer. Nearly the only chips used besides standard memory parts are 11 ASICs (of four types). Special geometry data reformatting hardware on one ASIC greatly speeds and simplifies the data input pipeline. Floating-point performance is enhanced by another ASIC: a custom graphics microprocessor, with specialized graphics instructions and features. Screen primitive rasterization is carried out in parallel by five drawing ASICs, employing a new partitioning of the back-end rendering task. For typical rendering cases, the only system performance bottleneck is that intrinsically imposed by VRAM.

• Type: Conference
• Year: 1993
• Where: SIGGRAPH
• Authors: Michael F. Deering, Scott R. Nelson
• Keywords: 24-bit True Color, Back-end Rendering Task, Computer Graphics, Performance 3D Graphics, SIGGRAPH 1993