TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs

This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Soft Errors in such class of device platforms. We propose an exploration of the design space with respect to several parameters (e.g., area and recovery time) in order to select the most convenient way to apply this technique to the device under consideration. The application to a case study is presented and used to exemplify the proposed approach.

• Type: Conference
• Year: 2007
• Where: DFT
• Authors: Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio
• Keywords: DFT 2007, Partial Dynamic Reconfiguration, Programmable Gate Arrays, Triple Modular Redundancy, VLSI