An efficient algorithm to verify generalized false paths

Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem because of the inherent computational cost, and because in practice false paths are not specified one full path at a time. Instead designers use generalized false paths, which represent a set of paths. For instance the SDC format (Synopsys Design Constraint) specifies false path exceptions using a “–from –through –to” syntax that applies on sets of pins, often using wildcards to denote these sets. This represents many (usually hundreds to thousands) actual full paths. This paper proposes a method to verify generalized false paths in a very efficient manner. It is shown to be about 10x faster than the current state-of-the-art, making false path verification an overnight task or less for multi-million gate designs. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids – Verification G...

• Type: Conference
• Year: 2010
• Where: DAC
• Authors: Olivier Coudert
• Keywords: Computer Architecture, DAC 2010, False Path, False Path Exceptions, Practice False Paths