A methodology to improve timing yield in the presence of process variations

The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing uncertainty in the performance of CMOS circuits. Accounting for the worst case values of all parameters will result in an unacceptably low timing yield. Design for Variability, which involves designing to achieve a given level of confidence in the performance of ICs, is fast becoming an indispensable part of IC design methodology. This paper1 describes a method to identify certain paths in the circuit that are responsible for the spread of timing performance. The method is based on defining a disutility function of the gate and path delays, which includes both the means and variances of the delay random variables. Based on the moments of this disutility function, an algorithm is presented which selects a subset of paths (called undominated paths) as being most responsible for the variation in timing performa...

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang
• Keywords: Computer Architecture, DAC 2004, Low Timing Yield, Path Delay, Timing Yield