ET
2002
14 years 6 months ago
2002
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
DFT
2004
IEEE
14 years 10 months ago
2004
IEEE
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
VTS
2005
IEEE
15 years 7 days ago
2005
IEEE
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...
ETS
2006
IEEE
15 years 22 days ago
2006
IEEE
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...