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2006
IEEE

On-Chip Time Measurement Architecture with Femtosecond Timing Resolution

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On-Chip Time Measurement Architecture with Femtosecond Timing Resolution
This paper presents a new on-chip time measurement architecture which is based on the Timeto-Digital Conversion (TDC) method that is capable of achieving a timing resolution of tens of femtoseconds without the use of external automatic test equipment (ATE). This is the highest temporal resolution that has been reported to-date and is achieved by the use of the homodyne technique. The proposed architecture has been designed using a 0.12
Matthew Collins, Bashir M. Al-Hashimi
Added 22 Aug 2010
Updated 22 Aug 2010
Type Conference
Year 2006
Where ETS
Authors Matthew Collins, Bashir M. Al-Hashimi
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