Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis

Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The reconfigurability of Field-Programmable Gate Arrays presents the opportunity to compensate for within-die delay variability. This paper presents three reconfiguration-based strategies for compensating within-die stochastic delay variability in FPGAs: reconfiguring the entire FPGA, relocating subcircuits within an FPGA, and reconfiguring signal paths within a design. The yield of each strategy is analysed and compared with worst-case design and statistical static timing analysis (SSTA). It is demonstrated that significant improvements in circuit yield and timing are possible using SSTA alone, and these improvements can be enhanced by employing reconfiguration-based techniques. Categories and Subject Descriptors B.6.1 [Integrated Circuits]: Design Styles—Logic arrays; B.7.1 [Integrated Circuits]: Types an...

• Type: Conference
• Year: 2007
• Where: FPGA
• Authors: N. Pete Sedcole, Peter Y. K. Cheung
• Keywords: Delay Variability, FPGA 2007, Hardware, Stochastic Delay Variability, Within-die Delay Variability