An Algorithm for Yield Improvement via Local Positioning and Resizing

The ability to improve the yield of integrated circuits through layout modification has been recognized and several techniques for yield enhanced routing and compaction have been developed. The approach described in this paper is aimed to improve the random defect limited yield of the VLSI design. The goal is achieved by increasing the design tolerance to short (extra material) and open (missing material) type defects. This approach and the suggested algorithm can be used as a post place and route step for improving catastrophic yield loss caused by the random defects. Keywords Yield, layout optimization, yield improvement.

• Type: Conference
• Year: 2006
• Where: CDES
• Authors: Vazgen Karapetyan
• Keywords: Catastrophic Yield Loss, CDES 2006, CDES 2007, Defect Limited Yield, Random Defects