TVLSI
2002
13 years 11 months ago
2002
A summary of electrical and optical approaches to clock distribution within high-performance microprocessors is presented. System-level properties of intrachip electrical clock dis...
CSREAESA
2004
14 years 25 days ago
2004
Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because the wires do not scale as fast as the device...
ASPDAC
2005
ACM
14 years 1 months ago
2005
ACM
— In this paper, a methodology for analyzing closed loop clock distribution and active deskewing networks is proposed. An active clock distribution and deskewing network is model...
ICCAD
1997
IEEE
14 years 3 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
DAC
1999
ACM
14 years 3 months ago
1999
ACM
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
— A formal methodology for the analysis of a closed loop clock distribution and active deskewing network is proposed. In this paper an active clock distribution and deskewing net...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
—In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthe...
ICCD
2001
IEEE
14 years 8 months ago
2001
IEEE
Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked...