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TODAES
2008

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Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming

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Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming

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Yu Hu, Yan Lin, Lei He, Tim Tuan

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» Simultaneous time slack budgeting and retiming for dualVdd FPGA power reduction

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Added	15 Dec 2010
Updated	15 Dec 2010
Type	Journal
Year	2008
Where	TODAES
Authors	Yu Hu, Yan Lin, Lei He, Tim Tuan

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