Leakage-and crosstalk-aware bus encoding for total power reduction

Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We introduce a new buffer design approach with selective use of high threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. The proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work. Categories and Subject Descriptors B.8.2 [Performance and Reliability]: Performance analysis General Terms Algor...

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw
• Keywords: Bus Encoding Algorithm, Bus Encoding Scheme, Bus Encoding Work, DAC 2004, Design Automation