— This paper presents a solution to the problem of reducing the power dissipated by a digital system containing an intellectual proprietary core processor which repeatedly execut...
Luca Benini, Giovanni De Micheli, Enrico Macii, Ma...
— In this paper, we propose a bus encoding scheme to minimize coupling effects which cause significant power consumption in the on-chip interconnects. The proposed bus encoding s...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed t...
Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, ...
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...