A 3D prototyping chip based on a wafer-level stacking technology

We have developed a new 3-dimensional stacking technology using wafer-to-wafer stacked method and evaluated the connectivity between TSV and micro-bump. The prototype 3-layer stacking device has been tried using our technology and the functional yield reached more than 60%. Using 8-inch wafer. We propose one of the design methodologies for a 3D stacked device.

• Type: Journal
• Year: 2009
• Where: ASPDAC
• Authors: Nobuaki Miyakawa
• Keywords: 3-layer Stacking, 8-inch Wafer, ASPDAC 2009, Hardware, Wafer-to-wafer Stacked Method