Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories

This paper proposes an adaptive multi-bit error correcting code for phase change memories that provides a manifold increase in the lifetime of phase change memories thereby making them a more viable alternative for DRAM main memory. A novel aspect of the proposed approach is that the error correction code (ECC) is adapted over time as the number of failed cells in the phase change memory accumulates. The operating system (OS) monitors the number of errors corrected on a memory line, and when the number of errors on a line begins to exceed the strength of the ECC present, the ECC strength is adaptively increased. As this happens, the performance of the memory system gracefully degrades because more storage is taken up by check bits rather than data bits thereby reducing the effective size of a cache line since less data can be brought to the cache on each read operation to the PCM main memory. Experimental results show that the lifetime of a phase change memory can be significantly ext...

• Type: Journal
• Year: 2011
• Where: VTS
• Authors: Rudrajit Datta, Nur A. Touba
• Keywords: Check Bits, Hardware, Memory Line, Phase Change Memory, VTS 2011