Enabling system-level modeling of variation-induced faults in networks-on-chips

Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 52%-81% inaccuracy. We propose an accurate circuit-level fault-modeling tool, which can be plugged into any system-level NoC simulator, quantify the system-level impact of PV-induced faults at runtime, pinpoint fault-prone router components that should be protected, and accurately evaluate alternative resilient multi-core designs. Categories and Subject Descriptors: B.8 [Hardware]: Performance and Reliability General Terms: Reliability, Measurement

• Type: Journal
• Year: 2011
• Where: DAC
• Authors: Konstantinos Aisopos, Chia-Hsin Owen Chen, Li-Shiuan Peh
• Keywords: Computer Architecture, Core Designs, DAC 2011, Hardware Performance, Reliability Measurement