Sciweavers

DAC
2011
ACM
12 years 12 months ago
Enabling system-level modeling of variation-induced faults in networks-on-chips
Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However,...
Konstantinos Aisopos, Chia-Hsin Owen Chen, Li-Shiu...
IEEEPACT
2009
IEEE
13 years 9 months ago
Core-Selectability in Chip Multiprocessors
Abstract--The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip ...
Hashem Hashemi Najaf-abadi, Niket Kumar Choudhary,...