We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the origin...
Supply voltage scaling has stagnated in recent technology nodes, leading to so-called “dark silicon.” In this paper, we investigate the limit of voltage scaling together with ...
Nathaniel Ross Pinckney, Korey Sewell, Ronald G. D...
Much recent research [8, 6, 7] suggests significant power and energy benefits of relaxing correctness constraints in future processors. Such processors with relaxed constraints ...
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
Full-chip thermal monitoring is an important and challenging issue in today’s microprocessor design. In this paper, we propose a new information-theoretic framework to quantitat...
Huapeng Zhou, Xin Li, Chen-Yong Cher, Eren Kursun,...
A scalable architecture to design high radix switch fabric is presented. It uses circuit techniques to re-use existing input and output data buses and switching logic for fabric c...
Sudhir Satpathy, Reetuparna Das, Ronald G. Dreslin...
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific h...
Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup ...
Due to the breakdown of Dennardian scaling, the percentage of a silicon chip that can switch at full frequency is dropping exponentially with each process generation. This utiliza...
Diverse IP cores are integrated on a modern system-on-chip and share resources. Off-chip memory bandwidth is often the scarcest resource and requires careful allocation. Two of t...
Min Kyu Jeong, Mattan Erez, Chander Sudanthi, Nige...
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...