We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the origin...
Large-scale process variations can significantly limit the practical utility of microelectro-mechanical systems (MEMS) for RF (radio frequency) applications. In this paper we desc...
Fa Wang, Gokce Keskin, Andrew Phelps, Jonathan Rot...
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce t...
Importance sampling is a popular approach to estimate rare event failures of SRAM cells. We propose to improve importance sampling by probability collectives. First, we use “Kul...
Fang Gong, Sina Basir-Kazeruni, Lara Dolecek, Lei ...
As technology scales and frequency increases, a new design style is emerging, referred to as hybrid designs, which contain a mixture of random logic and datapath standard cell com...
Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanat...
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu...
Stochastic device noise has become a significant challenge for high-precision analog/RF circuits, and it is particularly difficult to correctly include both white noise and flic...
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...
Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...