Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI

In this paper, we present a case study of our chip prototype of a 16-node 4x4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput for unicasts, multicasts and broadcasts. We first define and analyze the theoretical limits of a mesh NoC in latency, throughput and energy, then describe how we approach these limits through a combina

• Type: Journal
• Year: 2012
• Where: DAC
• Authors: Sunghyun Park, Tushar Krishna, Chia-Hsin Owen Chen, Bhavya Daya, Anantha Chandrakasan, Li-Shiuan Peh
• Keywords: CMOS, Computer Architecture, DAC 2012, Theoretical Limits, Throughput