A retargetable and accurate methodology for logic-IP-internal electromigration assessment

— A new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification stage, in the form of allowing arbitrary specifications (of lifetimes, temperatures, voltages and failure rates), as well as interoperability of IPs across foundries. The methodology is characterization- and reuse-based, and naturally incorporates complex effects such as clock gating and variable switching rates at different pins. The benefit from such a framework is demonstrated on a 28nm design, with close SPICEcorrelation and verification in a retargeted reliability condition.

• Type: Journal
• Year: 2015
• Where: ASPDAC
• Authors: Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella
• Keywords: ASPDAC 2015, Hardware