Transactional memory with strong atomicity using off-the-shelf memory protection hardware

This paper introduces a new way to provide strong atomicity in an implementation of transactional memory. Strong atomicity lets us offer clear semantics to programs, even if they access the same locations inside and outside transactions. It also avoids differences between hardware-implemented transactions and softwareimplemented ones. Our approach is to use off-the-shelf page-level memory protection hardware to detect conflicts between normal memory accesses and transactional ones. This page-level mechanism ensures correctness but gives poor performance because of the costs of manipulating memory protection settings and receiving notifications of access violations. However, in practice, we show how a combination of careful object placement and dynamic code update allows us to eliminate almost all of the protection changes. Existing implementations of strong atomicity in software rely on detecting conflicts by conservatively treating some non-transactional accesses as short transaction...

• Type: Conference
• Year: 2009
• Where: PPOPP
• Authors: Martín Abadi, Tim Harris, Mojtaba Mehrara
• Keywords: Page-level Memory Protection, Parallel Computing, PPOPP 2009, Strong Atomicity, Strong Atomicity Perform