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2006
IEEE

A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm

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A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm
In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round of the Rijndael algorithm, are generated in real-time by the key-scheduler module by expanding the initial secret key, thus reducing the amount of storage for buffering. Moreover, pipelining is used after each standard round to enhance the throughput. A prototype chip implemented using 0.35? CMOS technology resulted in a throughput of 232Mbps for iterative
Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mo
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2006
Where VLSID
Authors Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mohanty
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