TVLSI
2008
13 years 6 months ago
2008
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
VTS
2000
IEEE
13 years 11 months ago
2000
IEEE
A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real s...
VTS
2003
IEEE
14 years 2 days ago
2003
IEEE
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
ITC
2003
IEEE
14 years 2 days ago
2003
IEEE
Intermittent scan chain hold-time fault is discussed in this paper and a method to diagnose the faulty site in a scan chain is proposed as well. Unlike the previous scan chain dia...
ITC
2003
IEEE
14 years 2 days ago
2003
IEEE
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
ISQED
2006
IEEE
14 years 25 days ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
A methodology is presented for improving the amount of compression achieved by continuous-flow decompressors by using multiple ratios of scan chains to tester channels (i.e., expa...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper presents a new blocking logic to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and a...
DELTA
2008
IEEE
14 years 1 months ago
2008
IEEE
Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, ...
ICCD
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...