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VLSID
2004
IEEE

Designing Leakage Aware Multipliers

14 years 11 months ago
Designing Leakage Aware Multipliers
Power consumption has become a major design limiter. With the continued reduction of threshold voltages, optimizing leakage energy consumption is becoming increasingly important. Hence, the design of leakage-conscious memory and data path components is vital. This paper focuses on designing a 32-bit double precision multiplier, and shows how the appropriate choice of implementation primitives used in the design can provide significant leakage energy savings without much impact on performance.
M. DeRenzo, Mary Jane Irwin, Narayanan Vijaykrishn
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2004
Where VLSID
Authors M. DeRenzo, Mary Jane Irwin, Narayanan Vijaykrishnan
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