Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)

| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a given Prohibited Pattern Set (PPS). The design ensures desired pseudo-random quality of the test patterns generated. The experimental results con rm high quality of randomness while ensuring fault coverage close to the gures achieved with a typical Pseudo Random Pattern Generator (PRPG) designed around maximal length LFSR=CA. Compared to the conventional PRPG it incurs no additional cost.

• Type: Conference
• Year: 2002
• Where: VLSID
• Authors: Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri
• Keywords: Computer Architecture, Random Pattern Generator, Test Pattern Generator, Test Patterns, VLSID 2002