A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits

We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of different primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the various sets. The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time.

• Type: Conference
• Year: 2002
• Where: VLSID
• Authors: Irith Pomeranz, Sudhakar M. Reddy
• Keywords: Built-in Test Pattern, Computer Architecture, On-chip Test, Test Sets, VLSID 2002