Probabilistic counter updates for predictor hysteresis and stratification

Hardware counters are a fundamental building block of modern high-performance processors. This paper explores two applications of probabilistic counter updates, in which the output of a pseudo-random number generator decides whether to perform a counter increment or decrement. First, we discuss a probabilistic implementation of counter hysteresis, whereby previously proposed branch confidence and criticality predictors can be reduced in size by factors of 2 and 3, respectively, with negligible impact on performance. Second, we build a frequency stratifier by making increment and decrement probabilities functions of the current counter value. The stratifier enables a 4-bit counter to classify an instruction's Likelihood of Criticality with sufficient accuracy to closely approximate the performance of an unbounded precision classifier. Because probabilistic updates are both simple and effective, we believe these ideas hold great promise for immediate use by industry, perhaps enabli...

• Type: Conference
• Year: 2006
• Where: HPCA
• Authors: Nicholas Riley, Craig B. Zilles
• Keywords: Branch Confidence Predictors, Computer Architecture, Counter Increment, HPCA 2006, Probabilistic Counter Updates