On the Limits of Leakage Power Reduction in Caches

If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the fact that they account for the largest fraction of on-chip transistors, are the primary candidates for attacking the leakage problem. In this paper, we explore the limits in which existing circuit and architecture technologies may be able to address this growing problem. We find that by using perfect knowledge of the address trace, the circuit technologies of sleep and drowsy modes can be optimally combined to reduce the total leakage power due to the instruction cache down to a mere 3.6% of the unoptimized case. We also find that a simple next-line prefetching scheme can approximate this knowledge resulting in leakage power consumption of 8.9% of an equivalent unoptimized case.

• Type: Conference
• Year: 2005
• Where: HPCA
• Authors: Yan Meng, Timothy Sherwood, Ryan Kastner
• Keywords: Computer Architecture, HPCA 2005, Leakage Power Consumption, Leakage Power Dissipation, Total Leakage Power