Sciweavers

DATE
2005
IEEE
158views Hardware» more  DATE 2005»
14 years 5 months ago
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
14 years 5 months ago
Thermal-induced leakage power optimization by redundant resource allocation
Traditionally, at early design stages, leakage power is associated with the number of transistors in a design. Hence, intuitively an implementation with minimum resource usage wou...
Min Ni, Seda Ogrenci Memik
ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
14 years 5 months ago
Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates
Abstract— This paper quantifies the impact of threshold voltage variation on aging-related hard failure rates in a highperformance 65nm processor. Simulations show that threshol...
Brian Greskamp, Smruti R. Sarangi, Josep Torrellas
ISQED
2009
IEEE
124views Hardware» more  ISQED 2009»
14 years 6 months ago
Revisiting the linear programming framework for leakage power vs. performance optimization
— This paper revisits and extends a general linear programming(LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgateb...
Kwangok Jeong, Andrew B. Kahng, Hailong Yao
HPCA
2005
IEEE
14 years 11 months ago
On the Limits of Leakage Power Reduction in Caches
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the f...
Yan Meng, Timothy Sherwood, Ryan Kastner