Hardware design of a Binary Integer Decimal-based floating-point adder

Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P754). In this paper, we present a novel algorithm and hardware design for a DFP adder. The adder performs addition and subtraction on 64-bit operands that use the IEEE P754 binary encoding of DFP numbers, widely known as the Binary Integer Decimal (BID) encoding. The BID adder uses a novel hardware component for decimal digit counting and an enhanced version of a previously published BID rounding unit. By adding more sophisticated control, operations are performed with variable latency to optimize for common cases. We show that a BID-based DFP adder design can be achieved with a modest area increase compared to a single 2-stage pipelined 64-bit fixed-point multiplier. Over 70% of the BID adder’s area is due the 64-bit fixed-point multiplier, which can be shared with a binary floating-point multiplier and hard...

• Type: Conference
• Year: 2007
• Where: ICCD
• Authors: Charles Tsen, Sonia Gonzalez-Navarro, Michael J. Schulte
• Keywords: 64-bit Fixed-point Multiplier, BID Adder Area, DFP Adder Design, Hardware, ICCD 2007