Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits

Hybrid nanoelectronics are emerging as one viable option to sustain the Moore’s Law after the CMOS scaling limit is reached. One main design challenge in hybrid nanoelectronics is the interface (named as demux) between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in CMOS domain. The prior work on demux design use a single type of devices to realize the demultiplexing function, but hardly provides a satisfactory solution. This work proposes to combine resistor with FET to implement the demux, leading to the so-called hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices well complement each other to improve the overall demux design effectiveness. Furthermore, the effects of resistor conductance variability are analyzed and evaluated based on computer simulations.

• Type: Conference
• Year: 2007
• Where: ICCD
• Authors: Shu Li, Tong Zhang
• Keywords: CMOS Scaling Limit, Hardware, Hybrid Nanoelectronics, ICCD 2007, Resistor Conductance Variability