GPE: A New Representation for VLSI Floorplan Problem

In this paper, we propose a new representation of VLSI floorplan and building block problem. The representation is the generalization of Polish expression [1]. By proposing a new relational operator, the representation can efficiently reuse some area that cannot be utilized if only having vertical and horizontal operators defined in Polish expression, and is able to present non-slicing structural floorplan. The experimental results show that the representation achieves promising area utilization in commonly used MCNC benchmark circuits.

• Type: Conference
• Year: 2002
• Where: ICCD
• Authors: Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang
• Keywords: Hardware, ICCD 2002, Non-slicing Structural Floorplan, Polish Expression, VLSI Floorplan