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ICCD
2001
IEEE

MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor

14 years 7 months ago
MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor
This paper describes an experiment which aims to reveal the potential impact on performance yielded by augmenting a TriMedia-CPU64 processor with a multiple-context FPGA core. We first propose an extension of the TriMediaCPU64 architecture, which consists of a Reconfigurable Functional Unit and its associated instructions. Then, we address the decoding of variable-length codes on such extended TriMedia and describe the architecture and FPGAimplementation of a Variable-Length Decoder (VLD) computing facility. When mapped on an ACEX EP1K100 FPGA, the proposed VLD exhibits a latency of cycles. Preliminary results indicate that by configuring each of the VLD and 1-D IDCT (which is described elsewhere) facilities on a different FPGA context, and by activating the contexts as needed, the augmented TriMedia can perform macroblock parsing followed up by pel reconstruction with an improvement of ¾¼ ¾ ±over the standard TriMedia.
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis,
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2001
Where ICCD
Authors Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
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