A new incremental placement algorithm and its application to congestion-aware divisor extraction

— This paper presents two contributions. The first is an incremental placement algorithm for placement-aware logic synthesis along with a proof of optimality. The algorithm can efficiently compute the optimum location for a newly introduced node in a network that minimizes the incremental increase in the total half-perimeter wire-length of the network. The algorithm can be applied in a variety of placement-aware optimization contexts. The second contribution is a specific application of this algorithm to placement-aware common divisor extraction. We evaluate the effectiveness of the proposed extraction procedure by using it in an otherwise non-placement-aware flow with two different final placers. The first flow uses an industrial congestiondriven placer and results in an average reduction of 21% in congestion as measured by the global router. The second flow uses an academic wire-length-driven placer and results in an average reduction of 11% for a tool-specific measure of ...

• Type: Conference
• Year: 2004
• Where: ICCAD
• Authors: Satrajit Chatterjee, Robert K. Brayton
• Keywords: Average Reduction, Common Divisor Extraction, Hardware, ICCAD 2004, Incremental Placement Algorithm