Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication

Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration of multi-cycle on-chip communication at the high level. In this paper, we present a new architectural synthesis system integrated with global placement, named MCAS (Multi-Cycle Architectural Synthesis), on top of the recently-proposed Regular Distributed Register (RDR) micro-architecture [3]. The RDR architecture provides a regular synthesis platform for supporting multi-cycle communication. Novel architectural synthesis algorithms that integrate high-level synthesis with global placement have been developed in MCAS, including scheduling-driven placement and distributed controller generation, etc. Experimental results show that our methodology can achieve a clock period improvement of 31% and a total latency improvement of 24% on average compared to the conventional architectural synthesis flow.

• Type: Conference
• Year: 2003
• Where: ICCAD
• Authors: Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
• Keywords: Architectural Synthesis, Architectural Synthesis Algorithms, Conventional Architectural Synthesis, Hardware, ICCAD 2003