Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion

In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and developconcurrent repeater and FF insertion schemes. Considering structural.interconnects, layer assignment and concurrent repeater and FF insertion for delay specification, we develop a cycle-accurate microarchitecture-level interconnect power simulation'. The simulation reduces the over-estimationby'up to 2.46X compared to power estimationhasedon purelystochasticinterconnectsand fixed switching factor. Furthermore, we show that interconnect pipelining his a lower IPC but can improve throughput by up to 2.03X. This indicates that the traditional design flow optimizing IPC and clock frequency separarely may no longer be valid.

• Type: Conference
• Year: 2003
• Where: ICCAD
• Authors: Weiping Liao, Lei He
• Keywords: FF Insertion Schemes, Hardware, ICCAD 2003, Interconnect Power Modeling, Interconnect Power Simulation