Conflict driven techniques for improving deterministic test pattern generation

This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic decision ordering, conflict driven recursive learning and conflict learning. An important feature shared by all these techniques is that they are triggered by the occurrence of a conflict in the generation of tests. Hence, they are not active all the time nor for all the faults. This feature allows the ATPG system that uses these techniques to resolve hard-to-resolve faults with far fewer backtracks and leaves the system as efficient as before in the absence of conflicts. We have incorporated these techniques into a commercial D-algorithm based ATPG tool. The experimental results on full scan versions of ITC’99 benchmark circuits demonstrate an improvement of the ATPG system both in the number of aborted faults and in test generation time.

• Type: Conference
• Year: 2002
• Where: ICCAD
• Authors: Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
• Keywords: Aborted Faults, Hardware, ICCAD 2002, Test Generation Time, Test Pattern Generation