TCAD
2010
13 years 6 months ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
DATE
2010
IEEE
14 years 3 months ago
2010
IEEE
Model checking techniques are promising for automated generation of directed tests. However, due to the prohibitively large time and resource requirements, conventional model chec...
ICCAD
2002
IEEE
14 years 8 months ago
2002
IEEE
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
VLSID
2009
IEEE
15 years 3 days ago
2009
IEEE
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...