Scheduling Synchronous Elastic Designs

Asynchronous and latency-insensitive circuits offer a similar form of elasticity that tolerates variations in the delays of communication resources of a system. This flexibility comes at the expense of including a control layer that synchronizes the flow of information. This paper proposes a method for eliminating the complexity of the control layer, replacing it by a set of iterative schedulers that decide when to activate computations. Unlike previous approaches, this can be achieved with low complexity algorithms and without extra circuitry.

• Type: Conference
• Year: 2009
• Where: ACSD
• Authors: Josep Carmona, Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky
• Keywords: ACSD 2009, Control Layer, Hardware, Latency-insensitive Circuits, Low Complexity Algorithms