Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories

Hybrid CMOS/non-CMOS memories, in short hybrid memories, have been lauded as future ultra-capacity data memories. Nonetheless, such memories are going to suffer from high degree of cluster faults, which impact their reliability. This paper proposes two modified Redundant Residue Number Systems (RRNS) based error correcting codes to tolerate cluster faults in hybrid memories, namely (i) Three Non-Redundant Moduli RRNS (3NRM-RRNS) and (ii) Two Non-Redundant Moduli RRNS (2NRM-RRNS). Experimental results and analysis show that 3NRM-RRNS and 2NRM-RRNS possess competitive error correction capability to that of Reed-Solomon (RS) and conventional RRNS (C-RRNS), but at lower cost (reduced code size, lower performance penalty). E.g., for 16

• Type: Conference
• Year: 2009
• Where: DFT
• Authors: Nor Zaidi Haron, Said Hamdioui
• Keywords: DFT 2009, Hardware, Hybrid Memories, Non-Redundant Moduli RRNS, Short Hybrid Memories