A novel sequential circuit optimization with clock gating logic

— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the clock-gating conditions and the next-state function of a Flip-Flop (FF) are correlated and can be used for sequential optimization. We show that the implementation of the next-state function of any FF can be just an inverter if the clock signal is appropriately gated. By exploiting the flexibility between the clock-gating conditions and the nextstate function, we propose an iterative optimization technique to minimize the overall timing.

• Type: Conference
• Year: 2008
• Where: ICCAD
• Authors: Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang
• Keywords: Certain Clock-gating Conditions, Clock Signal, Clock-gating Conditions, Hardware, ICCAD 2008