Importance sampled circuit learning ensembles for robust analog IC design

This paper presents ISCLEs, a novel and robust analog design method that promises to scale with Moore’s Law, by doing boosting-style importance sampling on digital-sized circuits to achieve the target analog behavior. ISCLEs consists of: (1) a boosting algorithm developed specifically for circuit assembly; (2) an ISCLEs-specific library of possible digital-sized circuit blocks; and (3) a recently-developed multi-topology sizing technique to automatically determine each block’s topology and device sizes. ISCLEs is demonstrated on design of a sinusoidal function generator and a flash A/D converter, showing promise to robustly scale with shrinking process geometries. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles, B.7.2: Design Aids

• Type: Conference
• Year: 2008
• Where: ICCAD
• Authors: Peng Gao, Trent McConaghy, Georges G. E. Gielen
• Keywords: Digital-sized Circuit, Hardware, ICCAD 2008, RObust Analog Design, Target Analog Behavior