Instruction Scheduling for Variation-Originated Variable Latencies

The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay also has variations. Recently, variable latency adders and long latency adders are proposed to manage the variation problem. Unfortunately, replacing a variation-affected adder with the long latency one has severe impact on processor performance. In order to maintain performance, the present paper proposes an instruction scheduling technique considering instruction criticality. By issuing and executing only uncritical instructions in the long latency ALU, we can maintain processor performance. From detailed simulations, we find that the proposed scheduling technique improves processor performance by 12.5% on average over the conventional scheduling and that performance degradation from a variation-free processor is only 4.0% on average, when 2 of 4 ALU’s are affected by variations.

• Type: Conference
• Year: 2008
• Where: ISQED
• Authors: Toshinori Sato, Shingo Watanabe
• Keywords: Hardware, ISQED 2008, Latency Adders, Long Latency, Processor Performance