Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This i...
An efficient frequency-based clock analysis method: CSAV is proposed in this paper. It computes the circuit response by first solving the state equation in frequency domain, and...
— The dominant substrate noise coupling mechanism is determined for multiple switching gates based on a physically intuitive model. The model exhibits reasonable accuracy as comp...
Emre Salman, Eby G. Friedman, Radu M. Secareanu, O...
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay also has variat...
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
Large-scale process fluctuations (particularly random device mismatches) at nanoscale technologies bring about highdimensional strongly nonlinear performance variations that canno...
In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A currentstarved ...
The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or vo...
Udo Sobe, Karl-Heinz Rooch, Andreas Ripp, Michael ...
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...