A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing

In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation effects at the design stage to avoid excessive performance and power penalties. Buffer insertion and driver sizing (BIDS) techniques are widely used in design flow due to their simplicity and effectiveness in improving metrics such as power, performance and noise. In this paper, we propose a fuzzy optimization technique to perform variation aware Buffer insertion and driver sizing at the network level. Previous variation aware techniques for buffer insertion, processes individual nets in a critical first fashion, which can result in severe over-buffering. Hence, we formulate the variation aware BIDS problem as a fuzzy piece-wise linear program to maximize variation resistance in the presence of delay, power and noise constraints. The uncertainty due to process variations in circuit delay is modeled using fuz...

• Type: Conference
• Year: 2008
• Where: ISVLSI
• Authors: Venkataraman Mahalingam, Nagarajan Ranganathan
• Keywords: Buffer Insertion, ISVLSI 2008, Variation Aware Bids, Variation Aware Buffer, VLSI