ISVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
ISVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
ISVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
Re-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is b...
ISVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large cap...
ISVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
ISVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS pro...
ISVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
ISVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
ISVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
ISVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires ...